1. Technical Field
The present invention relates generally to a solid state storage system, and more specifically, to a solid state storage system for using a memory area uniformly and a method of controlling the same.
2. Related Art
Generally, non-volatile memory is used as storage memory for most portable information devices. Recently, SSDs (Solid State Drive) using a NAND flash memory have come into the market. The SSDs are being used as substitutes for HDDs (Hard Disk Drive) in PCs (Personal Computer). Due to this shift in the market, SSDs are expected to rapidly erode the market share of HDDs.
A solid state storage system using the NAND flash memory includes a memory area composed of a plurality of blocks that include a plurality of pages. Due to the characteristics of the NAND flash memory, data programming is performed according to a page-unit, while updating or erasing of the data is performed according to a block-unit. That is, to update the contents in a page that is storing predetermined data, the entire block including the corresponding page must be erased first and then subsequently perform the programming for the pages. Therefore, it is known that the lifetime (for wearing limit) for a flash memory unit is generally limited by the frequency of use of the block, for example, the erase cycle or the erase count.
FIGS. 1A and 1B are graphs showing examples of when a specific block or a specific memory area is excessively used in a solid state storage system in the conventional art. The X-axis represents a memory address and the Y-axis represents an erase count in the graphs.
Referring to the graph of FIG. 1A, shown is an example of when the memory area between the 1500 address and the 2000 address is excessively used as compared to the other memory areas. Referring to the graph of FIG. 1B, shown is when the memory areas of specific addresses (for convenience, ath address and bth address are illustrated as examples) are excessively used, despite the fact that the areas of other addresses still maintain a fresh memory state. Due to the excessive use, an error is generated in the solid state storage system at the indicated memory areas.
As described, it is known that depending on the types of cells included in the flash memories, the lifetime of the cells is reached after a certain number of operations. For Example, when an SLC (Single Level Cell) is erased about 100,000 times and an MLC (Multi Level Cell) is erased about 5000 to 10,000 times, the lifetime of the cells may be exceeded. Therefore, it is important to maintain the flash memory such that all memory areas are uniformly used in order to effectively use SSDs for commercial purposes.
To address these issues, the main controller of a solid state storage system performs wear-leveling for blocks so that the use frequency of all blocks of the memory areas is maintained appropriately and the memory areas are used uniformly; however, such operations increase the load of the main controller and may contribute to performance deterioration of the entire solid state storage system.